The Fastbus interface

The digitization/acquisition cycle starts when the interface receives a trigger. The same trigger is sent to the IRQA interrupt of the CPU. Therefore the acquisition program generates a clock signal which allows to select the channel to be converted and to start the conversion.

When the ADC conversion is finished, an End-Of-Conversion signal is sent to the second CPU interrupt (IRQB) and the acquisition program generates the clock signal for the following selection.

The initialization of all multiplexers requires 5.5 $\mu$s; the selection of the channel 2.14 $\mu$s; the conversion readout 3.18 $\mu$s.

The channels to be converted are selected in a given order which does not follow their natural numbering.