The readout electronics is based on preamplifiers and Fastbus modules described in ref. [5] and ref. [6]. These modules receive the differential signals from preamplifiers and provide the shaping, the track & hold, the multiplexing and the 12-bit digitization of the signals.
The original design of these modules (FEMC) was modified by the Electronic Pool of INFN Pavia [7]. A trigger section with a double threshold discriminator was added and the original optical transmitter for the readout was replaced by a Latch circuit.
Data are sent to an interface which contains the control logic and is directly fed to the VME CPU DSP56 that is used for acquisition.
In fig. 4 the block diagram of the readout electronics is shown.
