The Latch circuit [7] replaces the optical transmitter of the FEMC module allowing the VME acquisition.
It consists of two 74FCT533 latches. The Fastbus modules are equipped with a 12-bit ADC, thus the readout is made for a pair of modules at a time, in such a way that all the 24 bits/word of the CPU DSP56 are filled: the 12-bit data of the first module fill the low significant bits (LSB) and the 12-bit data of the second module fill the most significant bits (MSB). This is obtained by doubling the latch system.