FEMC modules

There are four FEMC Fastbus modules used in the electronics set-up. Each module implements 80 channels divided into 5 groups (rows). Each channel is equipped with a hybrid shaper, consisting of a (RC)

CR filter. It is followed by a hold circuit allowing the 80 signals to be multiplexed and serially digitized by a single 12-bit ADC DATEL 810 with 2 $\mu$ s conversion time. In fig. 7 the block diagram of the shaper is shown.

**Figure 7:** Block diagram of the shaper
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An auto-trigger line has been obtained by taking out the signal from the first stage of each shaper (pin #5). This signal is sent to an on-board discriminator (fig. 8) with a double circuit allowing to set two different threshold levels: a High Level Threshold (HLT) and a Low Level Threshold (LLT).

The output signals of each row of shapers (16 channels) are OR-ed to generate a HLT trigger and a LLT trigger. The delay of the auto-trigger with respect to a signal injected into the test line of the preamplifier is 160 ns.

The auto-trigger signals are combined into external modules to provide two experimental triggers, one for low energy protons and one for pions and high energy protons. These triggers also generate the track & hold signal.

**Figure 8:** Double threshold discriminator
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**Figure 9:** A step pulse is injected directly into the shaper input. Up: output signal from the pin #5 of the shaper. Down: output signal after the differential CR stage of the discriminator.
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Fig. 9 shows the output of the first stage of the shaper (up) which is differentiated (down) and sent to the discriminator.

**Figure 10:** The output signal obtained from the hybrid shaper (pin #12).
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The output signal of the shaper is bipolar (fig. 10) with the following characteristics:

The arrival of an experimental trigger makes the hold active and the signal is stored for conversion (fig. 11).

The hold must start in correspondence to the signal maximum amplitude, so a Timing Unit is used to generate the proper delay to the experimental trigger.

**Figure 11:** The signal stored by the hold circuit. Signals can be stored up to 3 ms with negligible attenuation
$\begin{figure} \begin{center} \epsfig {file=photo_holded.eps, width=10cm}\end{center}\end{figure}$